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SNEHIL VERMA

ABOUT ME

Tech-savvy

Photo of Me

I am an M.Sc. student in Electrical & Computer Engineering at the University of Texas at Austin. My advisor is Prof. Lizy K. John, and I am affiliated with the Laboratory for Computer Architecture (LCA). My research focuses on Computer Architecture, specifically on performance evaluation on machine learning workloads. I completed my bachelor's degree in Electrical Engineering from the Indian Institute of Technology Kanpur in 2014. Please click on the Résumé tab(s) above to know more.

Master's: The University of Texas at Austin

Major

Electrical and Computer Engineering
Track: Architecture, Computer Systems, and Embedded Systems (ACSES)

Bachelor's: Indian Institute of Technology Kanpur

Major

Electrical Engineering

Minor

Computer Systems
PORTFOLIO

Projects

Here are some of my research and industrial projects.
Hover over the images to know more.


Samsung
Affiliated with several teams: PPA (Power, Performance, and Area), Architecture, ML Strategic Planning, and Workload Characterization.
Metrics ML
Publication Presentation
FastPath, ISPASS'19: Proposed a new metric for benchmarking ML workloads from the perspective of comparing training hardware.
MLPerf GTC
Presentation Slides
NVIDIA GTC'19: An extensive study on the impact of hardware infrastructure choices on deep learning performance for training.
Kernel Fusion
Presentation (long) Presentation (short)
Integrated our C++/CUDA extensions, performing kernel fusion, with PyTorch to optimize Convolutional Seq-to-Seq Learning model.
HBM Ligra
Report Presentation
Incorporated a novel fine-grain static graph placement technique on Ligra that takes decisions based on natural properties of the graph.
DFCM++
Publication Presentation Poster
CVP-1, ISCA'18: Enhanced the existing DFCM predictor achieving an IPC improvement of 28.1% over the baseline and 40.2% over the base DFCM.
NVM
Presentation Term Paper
Studied emerging flexible NVMs encompassing their operating principles and some common architectures. Additionally, performed a literature survey on various binary metal-oxide resistive switching RAMs, their switching mechanisms, designs, and electrical characteristics.
CARP 2.0
Report Presentation (TAMU) Presentation (IITK)
Proposed and modeled Coherence-Aware Reuse Prediction on ZSim that achieved a speedup of 20% over LRU when evaluated on the PARSEC benchmark suite.
PLL
Report Presentation
Designed a stable PLL with low power linear Current Starved VCO which consumed a maximum power of 182uW.
LNA
Studied the noise cancellation techniques of inductorless LNAs, and effectively applied them to design a 2.4 GHz Inductorless LNA.
Verilog
Report
Implemented a threshold voltage based BSIM4-like model on Verilog-A and extracted parameters using IC-CAP simulation.
Folded Cascode
Report
Employed adaptive biasing to design a two-stage folded cascode OTA suitable for large capacitive loads.
DBMS
Designed a website implementing a miniature version of the railway inquiry system to handle standard queries.
MIMO
Term Paper
Conducted a literature survey on Multiple-Input Multiple-Output (MIMO) systems and its potential in 4G and 5G.
H_inf Controller
Report
Designed a H∞ controller and tuned it for desired performances in order to make the system as robust as possible.
SASTR
Presentation
Built an all-terrain vehicle capable of autonomous navigation using Embedded Systems and Google Maps API.

CONTACT

Where to find me?

Feel free to contact me.


2501 Speedway, EER 5.860, Austin, TX 78712
Phone: (+1) 737-217-5056
Email: snehilv@utexas.edu

Swing by for a cup of , or leave me a note.